Design-for-testability (“DFT”) techniques based on scan and automatic test pattern generation (“ATPG”) are commonly used as part of integrated circuit manufacturing to provide very high test coverage. For large circuits, however, the volume of test data required to test such circuits can cause a significant increase in test time and tester memory requirements. In order to cope with these challenges, various test data reduction schemes have been introduced. Some test data reduction schemes, for example, use on-chip decompression and compression hardware. By using such hardware, a tester can deliver test patterns in a compressed form, and the on-chip decompressor can expand (or decompress) the compressed test patterns into the actual data loaded into scan chains. The latter operation is possible because typically only a small number of bits in the decompressed test patterns are specified bits designed to target one or more specific faults in the integrated circuit. The remaining unspecified bits of the decompressed test pattern commonly comprise “don't care” bits and are randomly determined as a result of the decompressor structure. The high number of randomly filled test pattern bits, however, can cause excessive switching in the scan cells of the scan chains. This, in turn, often leads to undesirably high power consumption during the test procedure. Such power consumption can result in overheating or supply voltage noise—either of which can cause a device to malfunction, its permanent damage, or reliability degradation due to accelerated electro-migration. Accordingly, improved methods for generating test patterns that reduce the amount of power consumed during testing are desired.